EPM7256SQC208-7N vs EPM7256SQC208-10 Comparison

Detailed side-by-side comparison of EPM7256SQC208-7N by Altera and EPM7256SQC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7256SQC208-7N EPM7256SQC208-10
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.20 $11.20
Family MAX 7000S β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 256 256
Usable Gates 5,000 5,000
Logic Array Blocks (LABs) 16 16
User I/O Pins 164 β€”
Speed Grade -7 (7.5 ns pin-to-pin) β€”
Maximum Frequency 128.2 MHz β€”
Supply Voltage (VCC) 5 V β€”
Technology CMOS EEPROM β€”
Configuration Memory Non-volatile EEPROM (no external config needed) β€”
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP (SQC208)
Mounting Type Surface Mount Surface Mount
Operating Temperature Commercial (0C to +70C) 0C to +70C (commercial)
JTAG Interface IEEE 1149.1 boundary-scan (ISP capable) β€”
Minimum DC Input Voltage -0.5 V β€”
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns β€”
RoHS Status Compliant (N suffix = lead-free) [DATA_NEEDED: RoHS compliance status]
Pin-to-Pin Delay (tPD) 7.5 ns β€”
Open-Drain Output Optional per I/O pin β€”
Series β€” MAX 7000S
Number of I/O Pins β€” 164
Propagation Delay (tPD) β€” 10 ns
Counter Speed (fCNT) β€” Up to 175.4 MHz
Programmable Technology β€” EEPROM (in-system programmable)
JTAG Support (IEEE 1149.1) β€” Yes
PCI Compliance β€” PCI Local Bus Specification 2.2 compliant
MSL Level β€” 3 (168 hours)

Datasheets & Resources

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