EPM7256SQC208-7N vs EPM7256SQI208-10 Comparison

Detailed side-by-side comparison of EPM7256SQC208-7N by Altera and EPM7256SQI208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7256SQC208-7N EPM7256SQI208-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $27.20 $0.40
Family MAX 7000S β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 256 256
Usable Gates 5,000 5000
Logic Array Blocks (LABs) 16 β€”
User I/O Pins 164 β€”
Speed Grade -7 (7.5 ns pin-to-pin) β€”
Maximum Frequency 128.2 MHz β€”
Supply Voltage (VCC) 5 V β€”
Technology CMOS EEPROM CMOS EEPROM
Configuration Memory Non-volatile EEPROM (no external config needed) EEPROM (non-volatile)
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP (QFP208)
Mounting Type Surface Mount Surface Mount
Operating Temperature Commercial (0C to +70C) β€”
JTAG Interface IEEE 1149.1 boundary-scan (ISP capable) β€”
Minimum DC Input Voltage -0.5 V β€”
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns β€”
RoHS Status Compliant (N suffix = lead-free) [DATA_NEEDED: RoHS status]
Pin-to-Pin Delay (tPD) 7.5 ns β€”
Open-Drain Output Optional per I/O pin β€”
Device Family β€” MAX 7000 (EPM7256)
Logic Array Blocks β€” 16
Maximum User I/O Pins β€” 164
Propagation Delay (tPD) β€” 10 ns
Supply Voltage Range β€” 4.5 V to 5.5 V
In-System Programmable β€” Yes (IEEE 1149.1 JTAG)
Package Body Material β€” Plastic/Epoxy
Terminal Form β€” Gull Wing
Operating Temperature Range β€” -40 C to +85 C (Industrial)
JESD-30 Package Code β€” S-PQFP-G208
JESD-609 Terminal Finish Code β€” E3

Datasheets & Resources

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