EPM7256SRC208-10 vs EPM7256SQC208-7N Comparison
Detailed side-by-side comparison of EPM7256SRC208-10 by Intel and EPM7256SQC208-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7256SRC208-10
EPM7256SRC208-10 - MAX 7000S CPLD 256 Macrocell 10ns | Intel
EPM7256SRC208-10 ObsoleteAltera
EPM7256SQC208-7N
EPM7256SQC208-7N - MAX 7000S CPLD 256 Macrocell | Altera
EPM7256SQC208-7N ObsoleteSpecification Comparison
| Parameter | EPM7256SRC208-10 | EPM7256SQC208-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 256 | β |
| Number of Logic Array Blocks (LABs) | 16 | β |
| Number of Gates | 5000 | β |
| Number of User I/O Pins | 164 | β |
| Maximum Propagation Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | β |
| Programmable Type | In System Programmable (ISP, JTAG) | β |
| Configuration Technology | EEPROM | β |
| Package | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm | 208-pin PQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (TA, commercial) | Commercial (0C to +70C) |
| Terminal Form | Gull Wing | β |
| Package Shape | Square | β |
| Product Status | Obsolete | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Macrocells | β | 256 |
| Usable Gates | β | 5,000 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/O Pins | β | 164 |
| Speed Grade | β | -7 (7.5 ns pin-to-pin) |
| Maximum Frequency | β | 128.2 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Technology | β | CMOS EEPROM |
| Configuration Memory | β | Non-volatile EEPROM (no external config needed) |
| JTAG Interface | β | IEEE 1149.1 boundary-scan (ISP capable) |
| Minimum DC Input Voltage | β | -0.5 V |
| Input Undershoot Tolerance | β | -2.0 V for <100 mA, <20 ns |
| Pin-to-Pin Delay (tPD) | β | 7.5 ns |
| Open-Drain Output | β | Optional per I/O pin |