EPM7256SRC208-10 vs EPM7256SRC208-10N Comparison
Detailed side-by-side comparison of EPM7256SRC208-10 by Intel and EPM7256SRC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7256SRC208-10
EPM7256SRC208-10 - MAX 7000S CPLD 256 Macrocell 10ns | Intel
EPM7256SRC208-10 ObsoleteIntel
EPM7256SRC208-10N
EPM7256SRC208-10N - MAX 7000S CPLD 256 Macro | Intel
EPM7256SRC208-10N ObsoleteSpecification Comparison
| Parameter | EPM7256SRC208-10 | EPM7256SRC208-10N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $27.20 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 256 | β |
| Number of Logic Array Blocks (LABs) | 16 | β |
| Number of Gates | 5000 | β |
| Number of User I/O Pins | 164 | β |
| Maximum Propagation Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | β |
| Programmable Type | In System Programmable (ISP, JTAG) | β |
| Configuration Technology | EEPROM | β |
| Package | 208-pin RQFP (BFQFP) exposed pad, 28x28 mm | 208-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (TA, commercial) | 0C to +70C (commercial) |
| Terminal Form | Gull Wing | β |
| Package Shape | Square | β |
| Product Status | Obsolete | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (N suffix = lead-free) |
| Macrocells | β | 256 |
| Usable Gates | β | 5,000 |
| User I/O Pins | β | 164 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 100 MHz |
| Supply Voltage | β | 5.0 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Logic Levels | β | 5.0 V TTL/CMOS compatible |
| Number of Logic Array Blocks | β | [DATA_NEEDED: number of LABs] |
| Maximum User Flash Memory | β | [DATA_NEEDED: user flash memory] |