EPM7512BQC208-5 vs EPM7512BQC208-10 Comparison
Detailed side-by-side comparison of EPM7512BQC208-5 by Altera and EPM7512BQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7512BQC208-5
EPM7512BQC208-5 - MAX 7000B CPLD 512 Macro 176 IO | Altera
EPM7512BQC208-5 ObsoleteAltera
EPM7512BQC208-10
EPM7512BQC208-10 - 512-Macrocell MAX 7000B CPLD, 10ns, PQFP-208 | Altera (Intel)
EPM7512BQC208-10 NrndSpecification Comparison
| Parameter | EPM7512BQC208-5 | EPM7512BQC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $38.66 | $19.40 |
| Family | MAX 7000B | MAX 7000B |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/O Pins | 176 | β |
| Logic Array Blocks | 16 | β |
| Propagation Delay (tPD) | 5 ns | β |
| Internal Frequency | 163.9 MHz | β |
| Supply Voltage (VCCINT) | 2.375 V to 2.625 V (2.5 V nominal) | β |
| Programmable Type | In System Programmable (ISP) | In-System Programmable (EEPROM) |
| Configuration Memory | EEPROM (non-volatile) | β |
| Package | 208-pin PQFP (28x28 mm) | β |
| Package Code | FQFP / S-PQFP-G208 | β |
| Terminal Pitch | 0.5 mm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to 70C (commercial) | 0 C to +70 C (commercial) |
| JTAG Support | IEEE 1149.1 boundary-scan | β |
| Speed Grade | -5 (fastest MAX 7000B grade) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Series | β | MAX 7000B |
| Logic Elements / Blocks | β | 32 LABs (16 macrocells per LAB) |
| User I/Os | β | 176 |
| Propagation Delay (tpd) | β | 10 ns (max, pin-to-pin) |
| Internal Supply Voltage | β | 2.375 V to 2.625 V (nominal 2.5 V) |
| Package / Case | β | 208-pin PQFP (28x28 mm), S-PQFP-G208 |
| Architecture | β | CMOS, Multiple Array Matrix (MAX) second-generation |
| JTAG / Boundary Scan | β | IEEE Std 1149.1 compliant |
| MSL Level | β | [DATA_NEEDED: MSL Level] |