EPM7512BQC208-7 vs EPM7512BQC208-10 Comparison

Detailed side-by-side comparison of EPM7512BQC208-7 by Altera and EPM7512BQC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7512BQC208-7

EPM7512BQC208-7 - MAX 7000B CPLD 512 Macro Cells | Altera

EPM7512BQC208-7 Obsolete

Specification Comparison

Parameter EPM7512BQC208-7 EPM7512BQC208-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $19.40
Family MAX 7000B MAX 7000B
Device Type Complex Programmable Logic Device (CPLD) β€”
Macrocells 512 512
Usable Gates 10,000 10,000
User I/O Pins 176 β€”
Maximum Internal Frequency 90.1 MHz β€”
Propagation Delay (tPD) 7 ns β€”
Supply Voltage (Core) 2.375 V to 2.625 V (2.5 V nominal) β€”
Programmable Type In-System Programmable (ISP), EEPROM-based In-System Programmable (EEPROM)
Package 208-pin PQFP (28x28 mm) β€”
Package Code FQFP β€”
Terminal Form Gull Wing β€”
Operating Temperature 0C to 90C (commercial) 0 C to +70 C (commercial)
Mounting Type Surface Mount Surface Mount
Logic Family CMOS β€”
ECCN 3A991 β€”
RoHS Status [DATA_NEEDED: RoHS status] unknown
Configuration Retention Non-volatile (no external configuration device required) β€”
Series β€” MAX 7000B
Logic Elements / Blocks β€” 32 LABs (16 macrocells per LAB)
User I/Os β€” 176
Propagation Delay (tpd) β€” 10 ns (max, pin-to-pin)
Internal Supply Voltage β€” 2.375 V to 2.625 V (nominal 2.5 V)
Package / Case β€” 208-pin PQFP (28x28 mm), S-PQFP-G208
Architecture β€” CMOS, Multiple Array Matrix (MAX) second-generation
JTAG / Boundary Scan β€” IEEE Std 1149.1 compliant
MSL Level β€” [DATA_NEEDED: MSL Level]

Datasheets & Resources

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