EPM9320ALC84-15 vs EPM9320LC84-20 Comparison

Detailed side-by-side comparison of EPM9320ALC84-15 by Altera and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320ALC84-15 EPM9320LC84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $9.75
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 β€”
Propagation Delay (tPD) 16 ns 16 ns
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) β€”
User I/O 56 β€”
Logic Array Blocks (LABs) 16 β€”
Technology CMOS, EEPROM-based configuration β€”
Package 84-pin PLCC (S-PQCC-J84, J-lead) PLCC-84 (Plastic Leaded Chip Carrier)
Mounting Type Through-hole / socket β€”
Programming Interface JTAG (IEEE 1149.1) / ISP β€”
Operating Temperature -40C to +85C (industrial) 0 C to 70 C
RoHS Status [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status]
Moisture Sensitivity Level (MSL) MSL-3 (168 hours per fpgalink.com) β€”
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] β€”
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) β€”
Device Type β€” CPLD - Complex Programmable Logic Device
User I/Os β€” 60
Logic Family β€” CMOS (EEPROM-based)
Pins β€” 84
Internal Counter Frequency β€” 118 MHz
Supply Voltage β€” 5.0 V
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Dedicated Inputs β€” 4 (global clock / clear / OE)
Architecture β€” Multiple Array MatriX (MAX), 3rd generation
PCI Compliance β€” PCI Local Bus Specification Rev. 2.2

Datasheets & Resources

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