EPM9320ARI208-10 vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320ARI208-10 by Intel and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9320ARI208-10
EPM9320ARI208-10 - MAX 9000 CPLD 320 Macrocell | Intel
EPM9320ARI208-10 ObsoleteAltera
EPM9320RC208-10
EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320RC208-10 NrndSpecification Comparison
| Parameter | EPM9320ARI208-10 | EPM9320RC208-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $26.40 |
| Programmable Type | In System Programmable (ISP) | β |
| Number of Macrocells | 320 | β |
| Number of Logic Elements/Blocks | 20 | β |
| Number of Gates | 6000 | β |
| Number of I/O | 132 | β |
| Propagation Delay tpd(1) Max | 10 ns | β |
| Maximum Counter Frequency | 144.9 MHz | β |
| Voltage Supply - Internal | 4.5 V to 5.5 V | β |
| Operating Temperature | -40 C to +85 C (TA) | Commercial (0C to +70C) - 'C' suffix |
| Mounting Type | Surface Mount | β |
| Package / Case | 208-BFQFP Exposed Pad | β |
| Supplier Device Package | 208-RQFP | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 | β |
| Product Status | Obsolete | β |
| Packaging | Tray | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 6,000 |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | [DATA_NEEDED: LAB count] |
| Package | β | 208-pin RQFP (RC) |
| Supply Voltage | β | 5 V |
| Speed Grade | β | -10 |
| Programming Interface | β | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | β | Yes (EPROM/EEPROM based) |
| Design Tool Support | β | MAX+PLUS II, Quartus (legacy) |
| Moisture Sensitivity Level (MSL) | β | 3 (168 Hours) |
| Lead Time | β | 1-7 days (per fpgalink listing) |