EPM9320ARI208-10 vs EPM9320RC208-20 Comparison
Detailed side-by-side comparison of EPM9320ARI208-10 by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9320ARI208-10
EPM9320ARI208-10 - MAX 9000 CPLD 320 Macrocell | Intel
EPM9320ARI208-10 ObsoleteAltera
EPM9320RC208-20
EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera
EPM9320RC208-20 ObsoleteSpecification Comparison
| Parameter | EPM9320ARI208-10 | EPM9320RC208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $21.90 |
| Programmable Type | In System Programmable (ISP) | β |
| Number of Macrocells | 320 | β |
| Number of Logic Elements/Blocks | 20 | β |
| Number of Gates | 6000 | β |
| Number of I/O | 132 | β |
| Propagation Delay tpd(1) Max | 10 ns | β |
| Maximum Counter Frequency | 144.9 MHz | β |
| Voltage Supply - Internal | 4.5 V to 5.5 V | β |
| Operating Temperature | -40 C to +85 C (TA) | 0 Β°C to 70 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Package / Case | 208-BFQFP Exposed Pad | β |
| Supplier Device Package | 208-RQFP | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 | β |
| Product Status | Obsolete | β |
| Packaging | Tray | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | 20 |
| Usable Gates | β | 6,000 |
| Maximum I/O Pins | β | 132 |
| Propagation Delay (tPD max) | β | 20 ns |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| Programming Technology | β | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | β | IEEE Std. 1149.1 (JTAG) |
| Package | β | 208-RQFP, exposed pad (208-BFQFP) |
| Architecture | β | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | β | CMOS, 5.0 V EEPROM |
| Reprogrammability | β | Yes, unlimited ISP cycles |