EPM9320GC280-20 vs EPM9560GC280-15N Comparison

Detailed side-by-side comparison of EPM9320GC280-20 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320GC280-20 EPM9560GC280-15N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $67.00 $125.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 320 β€”
Usable Gates 6000 (approx.) 12,000 (typical)
Logic Array Blocks (LABs) 20 (16 macrocells each, typical for MAX 9000) β€”
Maximum Operating Frequency 100 MHz (internal counter) β€”
Propagation Delay (tpd) 23 ns (approx., -20 speed grade) β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) β€”
Technology CMOS EEPROM β€”
In-System Programmability Yes (5.0-V ISP via JTAG) Yes (5.0-V ISP via JTAG)
JTAG Support IEEE Std. 1149.1 compliant β€”
Package 280-pin Ceramic Pin Grid Array (CPGA) CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Operating Temperature [DATA_NEEDED: operating temperature grade] β€”
Mounting Type Through-Hole (PGA socket) β€”
RoHS Status unknown β€”
Configuration Memory EEPROM (non-volatile, instant-on) β€”
Device Family β€” MAX 9000
Product Type β€” EE PLD / CPLD
Macrocell Count β€” 560
Propagation Delay (tPD) β€” 16.6 ns
Maximum Clock Frequency β€” 117.6 MHz
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
Maximum Supply Voltage β€” 5.25 V
Logic Technology β€” CMOS EEPROM
Boundary-Scan (JTAG) β€” IEEE Std. 1149.1 compliant
Package Code β€” PGA / CPGA280
Terminal Form β€” PIN/PEG
Operating Temperature Grade β€” Commercial
Architecture β€” Multiple Array MatriX (MAX) 3rd generation

Datasheets & Resources

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