EPM9320LC84-10 vs EPM9320ALC84-10 Comparison
Detailed side-by-side comparison of EPM9320LC84-10 by Intel and EPM9320ALC84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-10 | EPM9320ALC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $84.96 | $19.80 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | EPM9320 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | β |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 168 (varies by package) | 52 |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | β |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | β |
| Process Technology | 0.7 Β΅m CMOS EEPROM/UV-EPROM | β |
| Package | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount (PLCC socket also common) | Surface Mount / Through-Hole (PLCC socket) |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | [DATA_NEEDED: commercial/industrial grade] |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | β |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED] |
| Moisture Sensitivity Level (MSL) | MSL-3, 168 hours (per fpgalink listing) | β |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | β |
| Dedicated Inputs | β | 16 |
| Speed Grade | β | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Supply Voltage (VCCINT) | β | 5.0 V |
| In-System Programmability | β | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | β | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | β | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | β | Yes (EEPROM cell, powers up in known state) |
| Architecture | β | MAX (Multiple Array MatriX) with FastTrack Interconnect |