EPM9320LC84-10 vs EPM9320LC84-20 Comparison
Detailed side-by-side comparison of EPM9320LC84-10 by Intel and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-10 | EPM9320LC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $84.96 | $9.75 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | β |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (typical) | β |
| Logic Array Blocks (LABs) | 16 | β |
| Maximum User I/O Pins | 168 (varies by package) | β |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | β |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | β |
| Process Technology | 0.7 Β΅m CMOS EEPROM/UV-EPROM | β |
| Package | 84-pin PLCC (JEDEC MO-047) | PLCC-84 (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount (PLCC socket also common) | β |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | 0 C to 70 C |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | β |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | MSL-3, 168 hours (per fpgalink listing) | β |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | β |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| User I/Os | β | 60 |
| Logic Family | β | CMOS (EEPROM-based) |
| Pins | β | 84 |
| Propagation Delay (tPD) | β | 16 ns |
| Internal Counter Frequency | β | 118 MHz |
| Supply Voltage | β | 5.0 V |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | β | 4 (global clock / clear / OE) |
| Architecture | β | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | β | PCI Local Bus Specification Rev. 2.2 |