EPM9320LC84-10 vs EPM9400LC84-20 Comparison
Detailed side-by-side comparison of EPM9320LC84-10 by Intel and EPM9400LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9320LC84-10
EPM9320LC84-10 - MAX 9000 EPLD, 84-PLCC, 10ns | Intel / Altera
EPM9320LC84-10 NrndAltera
EPM9400LC84-20
EPM9400LC84-20 - MAX 9000 CPLD 400 Macrocells 5V ISP | Altera
EPM9400LC84-20 NrndSpecification Comparison
| Parameter | EPM9320LC84-10 | EPM9400LC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $84.96 | $38.50 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | β |
| Macrocells | 320 | 400 |
| Usable Gates | 6000 (typical) | 8,000 (6,000 to 12,000 typical range) |
| Logic Array Blocks (LABs) | 16 | β |
| Maximum User I/O Pins | 168 (varies by package) | β |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | β |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | β |
| Process Technology | 0.7 Β΅m CMOS EEPROM/UV-EPROM | CMOS EEPROM |
| Package | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount (PLCC socket also common) | Surface Mount (PLCC socket or SMT land pattern) |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | Commercial (0C to +70C) - assumed from -20 speed grade |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | β |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | MSL-3, 168 hours (per fpgalink listing) | β |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Architecture | β | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based |
| Flip-Flops | β | 580 |
| Maximum User I/O | β | 55 |
| Pin-to-Pin Propagation Delay | β | 20 ns (speed grade -20) |
| Maximum Counter Frequency | β | 144 MHz |
| Supply Voltage (VCCINT) | β | 5 V |
| I/O Voltage (VCCIO) | β | 3.3 V or 5 V (configurable) |
| In-System Programming | β | Yes (IEEE 1149.1 JTAG) |