EPM9320LC84-15 vs EPM9320GC280-15 Comparison
Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9320GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9320LC84-15
EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel
EPM9320LC84-15 ObsoleteAltera
EPM9320GC280-15
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9320LC84-15 | EPM9320GC280-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.95 | $92.50 |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Series | EPM9320 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Logic Array Blocks (LABs) | 20 | 20 (16 macrocells per LAB) |
| Propagation Delay (tPD) | 15 ns (max) | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 4.75 V to 5.25 V |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | β |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Mounting Type | Surface Mount | Through-hole (PGA socket) |
| Operating Temperature | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | β |
| Built-in Pull-up Resistors | Yes, on every I/O pin | β |
| Architecture Feature | Pin-locking across design iterations | β |
| RoHS Status | [DATA_NEEDED: confirm from manufacturer] | ROHS3 compliant (per fpgalink listing) |
| Architecture | β | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Pin-to-Pin Propagation Delay | β | 15 ns |
| Maximum Internal Frequency | β | 117.6 MHz |
| Maximum User I/O Pins | β | 164 |
| I/O Voltage Levels | β | 3.3 V or 5 V (configurable) |
| MSL Level | β | 3 (168 hours) |
| Technology Node | β | CMOS EEPROM, third-generation MAX |