EPM9320LC84-15 vs EPM9320LI84-20N Comparison
Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9320LI84-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-15 | EPM9320LI84-20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.95 | $9.75 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 to 12,000 |
| Logic Array Blocks (LABs) | 20 | β |
| Propagation Delay (tPD) | 15 ns (max) | 20 ns (speed grade -20) |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | β |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | β |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | β |
| Built-in Pull-up Resistors | Yes, on every I/O pin | β |
| Architecture Feature | Pin-locking across design iterations | β |
| RoHS Status | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS compliance status] |
| User I/O Pins | β | 60 |
| Total Pins | β | 84 |
| Pin-to-Pin Delay | β | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | β | 118 MHz |
| Logic Family | β | CMOS, EEPROM-based |
| Supply Voltage | β | 5.0 V |
| Programming Interface | β | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |
| Process Technology | β | Advanced CMOS EEPROM |