EPM9320LC84-15 vs EPM9400LC84-15 Comparison
Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9400LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9320LC84-15
EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel
EPM9320LC84-15 ObsoleteAltera
EPM9400LC84-15
EPM9400LC84-15 - MAX 9000 CPLD 8K Gates 400 Macros | Altera
EPM9400LC84-15 ObsoleteSpecification Comparison
| Parameter | EPM9320LC84-15 | EPM9400LC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.95 | $23.10 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | β |
| Usable Gates | 6,000 | 8,000 |
| Logic Array Blocks (LABs) | 20 | β |
| Propagation Delay (tPD) | 15 ns (max) | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | β |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | IEEE Std. 1149.1 compliant (ISP) |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0C to +70C (Commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | β |
| Built-in Pull-up Resistors | Yes, on every I/O pin | β |
| Architecture Feature | Pin-locking across design iterations | β |
| RoHS Status | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS status] |
| Macro Cells | β | 400 |
| Logic Array Blocks | β | 25 |
| Maximum User I/Os | β | 59 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Speed Grade | β | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | β | 5.0 V |
| Input Logic Compatibility | β | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | β | EEPROM (non-volatile, in-system programmable) |
| Minimum VCCINT | β | 4.75 V |
| Programming Method | β | In-System Programmable via JTAG |