EPM9320LI84-20N vs EPM9320LC84-10 Comparison
Detailed side-by-side comparison of EPM9320LI84-20N by Altera and EPM9320LC84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LI84-20N | EPM9320LC84-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $84.96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6000 (typical) |
| User I/O Pins | 60 | β |
| Total Pins | 84 | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | 84-pin PLCC (JEDEC MO-047) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | β |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | β |
| Maximum Counter Frequency | 118 MHz | β |
| Logic Family | CMOS, EEPROM-based | β |
| Supply Voltage | 5.0 V | β |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Architecture | Multiple Array MatriX (MAX) - third generation | β |
| Process Technology | Advanced CMOS EEPROM | 0.7 Β΅m CMOS EEPROM/UV-EPROM |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | ROHS3 Compliant (per fpgalink listing) |
| Device | β | EPM9320 |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/O Pins | β | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | β | 10 ns |
| Maximum Frequency (fCNT) | β | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | β | 5.0 V (typical, see datasheet) |
| Mounting Type | β | Surface Mount (PLCC socket also common) |
| Configuration | β | Non-volatile EEPROM (instant-on, no boot PROM) |
| Moisture Sensitivity Level (MSL) | β | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | β | 1-7 days (per fpgalink listing) |