EPM9320LI84-20N vs EPM9320LC84-20 Comparison

Detailed side-by-side comparison of EPM9320LI84-20N by Altera and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320LI84-20N

EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera

EPM9320LI84-20N Obsolete
Altera
EPM9320LC84-20

EPM9320LC84-20 - MAX 9000 CPLD, 320 Macros, 84-PLCC | Altera

EPM9320LC84-20 Obsolete

Specification Comparison

Parameter EPM9320LI84-20N EPM9320LC84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $9.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 320 320
Usable Gates 6,000 to 12,000 β€”
User I/O Pins 60 β€”
Total Pins 84 β€”
Package PLCC-84 (Plastic Leaded Chip Carrier, J-lead) PLCC-84 (Plastic Leaded Chip Carrier)
Propagation Delay (tPD) 20 ns (speed grade -20) 16 ns
Pin-to-Pin Delay 16 ns (per DigChip spec block) β€”
Maximum Counter Frequency 118 MHz β€”
Logic Family CMOS, EEPROM-based CMOS (EEPROM-based)
Supply Voltage 5.0 V 5.0 V
Operating Temperature 0 C to +70 C (commercial) 0 C to 70 C
Programming Interface IEEE 1149.1 JTAG, in-system programmable β€”
Architecture Multiple Array MatriX (MAX) - third generation Multiple Array MatriX (MAX), 3rd generation
Process Technology Advanced CMOS EEPROM β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
User I/Os β€” 60
Pins β€” 84
Internal Counter Frequency β€” 118 MHz
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Dedicated Inputs β€” 4 (global clock / clear / OE)
PCI Compliance β€” PCI Local Bus Specification Rev. 2.2

Datasheets & Resources

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