EPM9320RC208-10 vs EPM9320RC208-15 Comparison
Detailed side-by-side comparison of EPM9320RC208-10 by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-10 | EPM9320RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $26.40 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | β |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Package | 208-pin RQFP (RC) | 208-pin RQFP (Power QFP) |
| Operating Temperature | Commercial (0C to +70C) - 'C' suffix | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | 5 V | 5.0 V |
| Speed Grade | -10 | β |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | β |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | β |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) | β |
| Lead Time | 1-7 days (per fpgalink listing) | β |
| Device Family | β | MAX 9000 |
| Macro Cells | β | 320 |
| Pin-to-Pin Propagation Delay | β | 15 ns (speed grade -15) |
| Maximum Clock Frequency | β | 117.6 MHz |
| Configuration Technology | β | EEPROM-based (non-volatile) |
| In-System Programmability | β | Yes (ISP via JTAG) |
| JTAG Interface | β | IEEE Std. 1149.1 |
| Package Type | β | 208-BFQFP Exposed Pad |
| Mounting Type | β | Surface Mount |
| Number of I/O Pins | β | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | β | [DATA_NEEDED: LAB count] |
| Lifecycle Status | β | Obsolete (PDN0706, 2007) |