EPM9320RC208-15 vs EPM9320RC208-20N Comparison

Detailed side-by-side comparison of EPM9320RC208-15 by Altera and EPM9320RC208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9320RC208-15

EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera

EPM9320RC208-15 Obsolete
Altera
EPM9320RC208-20N

EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera

EPM9320RC208-20N Obsolete

Specification Comparison

Parameter EPM9320RC208-15 EPM9320RC208-20N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Device Family MAX 9000 MAX 9000
Macro Cells 320 320
Usable Gates 6,000 6,000
Pin-to-Pin Propagation Delay 15 ns (speed grade -15) β€”
Maximum Clock Frequency 117.6 MHz β€”
Supply Voltage 5.0 V 5.0 V
Configuration Technology EEPROM-based (non-volatile) β€”
In-System Programmability Yes (ISP via JTAG) Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface IEEE Std. 1149.1 β€”
Package 208-pin RQFP (Power QFP) 208-pin RQFP (PowerQuad II)
Package Type 208-BFQFP Exposed Pad β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Number of I/O Pins [DATA_NEEDED: user I/O count] β€”
Logic Array Blocks [DATA_NEEDED: LAB count] 20
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lifecycle Status Obsolete (PDN0706, 2007) β€”
Logic Type β€” Complex Programmable Logic Device (CPLD)
Maximum Pin-to-Pin Delay (tPD) β€” 20 ns
Maximum Operating Frequency β€” 100 MHz
Configuration Memory β€” EEPROM (non-volatile)
User I/O Pins β€” 168
Lead Finish β€” [DATA_NEEDED: lead finish]
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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