EPM9320RC208-15 vs EPM9320RI208-20C Comparison

Detailed side-by-side comparison of EPM9320RC208-15 by Altera and EPM9320RI208-20C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RC208-15 EPM9320RI208-20C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $22.10
Device Family MAX 9000 β€”
Macro Cells 320 β€”
Usable Gates 6,000 6,000
Pin-to-Pin Propagation Delay 15 ns (speed grade -15) β€”
Maximum Clock Frequency 117.6 MHz β€”
Supply Voltage 5.0 V β€”
Configuration Technology EEPROM-based (non-volatile) β€”
In-System Programmability Yes (ISP via JTAG) Yes (5.0 V ISP via JTAG)
JTAG Interface IEEE Std. 1149.1 β€”
Package 208-pin RQFP (Power QFP) 208-pin RQFP (Plastic Quad Flat Pack)
Package Type 208-BFQFP Exposed Pad β€”
Mounting Type Surface Mount Surface Mount
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
Number of I/O Pins [DATA_NEEDED: user I/O count] β€”
Logic Array Blocks [DATA_NEEDED: LAB count] β€”
RoHS Status [DATA_NEEDED: RoHS status] β€”
Lifecycle Status Obsolete (PDN0706, 2007) β€”
Family β€” MAX 9000
Device Type β€” EE PLD / CPLD
Logic Elements / Macrocells β€” 320
Number of Flip-Flops β€” 484
Logic Array Blocks (LABs) β€” 16
Maximum Internal Clock Frequency β€” 100 MHz
Pin-to-Pin Propagation Delay (tPD) β€” 20 ns
Supply Voltage (VCCINT/VCCIO) β€” 5.0 V
I/O Voltage Tolerance β€” 3.3 V or 5.0 V
Programmable Interface β€” JTAG (IEEE Std. 1149.1) BST
Technology β€” CMOS EEPROM
Operating Temperature (Industrial) β€” -40C to +85C
Lead-Free / RoHS β€” Information not confirmed from verified data [DATA_NEEDED: RoHS status]

Datasheets & Resources

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