EPM9320RC208-15 vs EPM9320RI208-20N Comparison
Detailed side-by-side comparison of EPM9320RC208-15 by Altera and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320RC208-15
EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera
EPM9320RC208-15 ObsoleteAltera
EPM9320RI208-20N
EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera
EPM9320RI208-20N NrndSpecification Comparison
| Parameter | EPM9320RC208-15 | EPM9320RI208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9320) |
| Macro Cells | 320 | β |
| Usable Gates | 6,000 | β |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Technology | EEPROM-based (non-volatile) | β |
| In-System Programmability | Yes (ISP via JTAG) | Yes, 5.0 V ISP via JTAG |
| JTAG Interface | IEEE Std. 1149.1 | IEEE Std. 1149.1 compliant |
| Package | 208-pin RQFP (Power QFP) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Package Type | 208-BFQFP Exposed Pad | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | β |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Obsolete (PDN0706, 2007) | β |
| Logic Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | β | 320 |
| Flip-Flops | β | 484 |
| Propagation Delay (tPD) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| I/O Voltage Tolerance | β | 3.3 V or 5 V configurable |
| Package Lead Pitch | β | 0.500 mm |
| Number of Terminals | β | 208 |
| Operating Temperature Range | β | -40C to +85C (Industrial) |
| Configuration Memory | β | EEPROM (non-volatile) |
| Dedicated Input Pins | β | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | β | -0.5 V |
| Minimum DC Input on Dedicated Inputs | β | -0.3 V |
| Input Undershoot/ Overshoot | β | -2.0 V / 7.0 V for <20 ns (no-load) |