EPM9320RC208-20 vs EPM9320ARC208-10N Comparison
Detailed side-by-side comparison of EPM9320RC208-20 by Altera and EPM9320ARC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-20 | EPM9320ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $21.90 | $19.45 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | β |
| Logic Array Blocks (LABs) | 20 | 16 |
| Usable Gates | 6,000 | β |
| Maximum I/O Pins | 132 | β |
| Propagation Delay (tPD max) | 20 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| Programming Technology | EEPROM, in-system programmable (ISP) | β |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | 0C to +70C (Commercial) |
| Package | 208-RQFP, exposed pad (208-BFQFP) | 208-pin RQFP (BFQFP with exposed pad) |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | β |
| Process Technology | CMOS, 5.0 V EEPROM | β |
| Reprogrammability | Yes, unlimited ISP cycles | β |
| Macro Cells | β | 320 |
| Logic Gates | β | 6,000 gates |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency | β | 144.9 MHz |
| Supply Voltage (VCC) | β | 5 V |
| User I/O Pins | β | 168 |
| Dedicated Input Pins | β | 12 |
| Programming Interface | β | IEEE Std. 1149.1 JTAG |
| Configuration Memory | β | Non-volatile EEPROM |
| RoHS Status | β | Compliant (lead-free 'N' suffix) |