EPM9320RC208-20 vs EPM9320RI208-20N Comparison

Detailed side-by-side comparison of EPM9320RC208-20 by Altera and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RC208-20 EPM9320RI208-20N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $21.90 $0.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 320 320
Logic Array Blocks (LABs) 20 β€”
Usable Gates 6,000 β€”
Maximum I/O Pins 132 β€”
Propagation Delay (tPD max) 20 ns β€”
Supply Voltage (VCCINT) 4.75 V to 5.25 V β€”
Programming Technology EEPROM, in-system programmable (ISP) β€”
Boundary-Scan Interface IEEE Std. 1149.1 (JTAG) β€”
Operating Temperature 0 Β°C to 70 Β°C (commercial) β€”
Package 208-RQFP, exposed pad (208-BFQFP) 208-pin PQFP (Plastic Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Architecture Multiple Array Matrix (MAX), 3rd generation β€”
Process Technology CMOS, 5.0 V EEPROM β€”
Reprogrammability Yes, unlimited ISP cycles β€”
Device Family β€” MAX 9000 (EPM9320)
Logic Type β€” EEPROM-based Complex Programmable Logic Device (CPLD)
Flip-Flops β€” 484
Propagation Delay (tPD) β€” 20 ns
Supply Voltage (VCC) β€” 5.0 V
I/O Voltage Tolerance β€” 3.3 V or 5 V configurable
Package Lead Pitch β€” 0.500 mm
Number of Terminals β€” 208
Operating Temperature Range β€” -40C to +85C (Industrial)
In-System Programmability β€” Yes, 5.0 V ISP via JTAG
JTAG Interface β€” IEEE Std. 1149.1 compliant
Configuration Memory β€” EEPROM (non-volatile)
Dedicated Input Pins β€” 4 (low-skew global distribution)
Minimum DC Input on I/O Pins β€” -0.5 V
Minimum DC Input on Dedicated Inputs β€” -0.3 V
Input Undershoot/ Overshoot β€” -2.0 V / 7.0 V for <20 ns (no-load)
RoHS Status β€” [DATA_NEEDED: RoHS status]

Datasheets & Resources

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