EPM9320RC208-20N vs EPM9320ARC208-10N Comparison
Detailed side-by-side comparison of EPM9320RC208-20N by Altera and EPM9320ARC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320RC208-20N
EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera
EPM9320RC208-20N ObsoleteAltera
EPM9320ARC208-10N
EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera
EPM9320ARC208-10N ObsoleteSpecification Comparison
| Parameter | EPM9320RC208-20N | EPM9320ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $19.45 |
| Device Family | MAX 9000 | β |
| Logic Type | Complex Programmable Logic Device (CPLD) | β |
| Usable Gates | 6,000 | β |
| Macro Cells | 320 | 320 |
| Logic Array Blocks | 20 | β |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile) | Non-volatile EEPROM |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| User I/O Pins | 168 | 168 |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin RQFP (BFQFP with exposed pad) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'N' suffix) |
| Lead Finish | [DATA_NEEDED: lead finish] | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 6,000 gates |
| Logic Array Blocks (LABs) | β | 16 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Frequency | β | 144.9 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Dedicated Input Pins | β | 12 |
| Programming Interface | β | IEEE Std. 1149.1 JTAG |