EPM9320RC208-20N vs EPM9320RI208-20N Comparison
Detailed side-by-side comparison of EPM9320RC208-20N by Altera and EPM9320RI208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320RC208-20N
EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera
EPM9320RC208-20N ObsoleteAltera
EPM9320RI208-20N
EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera
EPM9320RI208-20N NrndSpecification Comparison
| Parameter | EPM9320RC208-20N | EPM9320RI208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $0.00 |
| Device Family | MAX 9000 | MAX 9000 (EPM9320) |
| Logic Type | Complex Programmable Logic Device (CPLD) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Usable Gates | 6,000 | β |
| Macro Cells | 320 | β |
| Logic Array Blocks | 20 | β |
| Maximum Pin-to-Pin Delay (tPD) | 20 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage | 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, 5.0 V ISP via JTAG |
| User I/O Pins | 168 | β |
| Package | 208-pin RQFP (PowerQuad II) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Finish | [DATA_NEEDED: lead finish] | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Macrocells | β | 320 |
| Flip-Flops | β | 484 |
| Propagation Delay (tPD) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| I/O Voltage Tolerance | β | 3.3 V or 5 V configurable |
| Package Lead Pitch | β | 0.500 mm |
| Number of Terminals | β | 208 |
| Operating Temperature Range | β | -40C to +85C (Industrial) |
| JTAG Interface | β | IEEE Std. 1149.1 compliant |
| Dedicated Input Pins | β | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | β | -0.5 V |
| Minimum DC Input on Dedicated Inputs | β | -0.3 V |
| Input Undershoot/ Overshoot | β | -2.0 V / 7.0 V for <20 ns (no-load) |