EPM9320RI208-20 vs EPM9320RC208-20 Comparison

Detailed side-by-side comparison of EPM9320RI208-20 by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RI208-20 EPM9320RC208-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.95 $21.90
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 320 320
Usable Gates 6,000 6,000
Propagation Delay (tPD) 20 ns β€”
Maximum Operating Frequency 100 MHz β€”
Supply Voltage (VCC) 5.0 V β€”
Logic Elements / LABs 20 Logic Array Blocks (16 macro cells each) β€”
Programmable Interconnect Programmable Interconnect Array (PIA) β€”
In-System Programmability Yes - IEEE 1149.1 JTAG, 5.0-V ISP β€”
Dedicated Input Pins 4 (low-skew global) β€”
User I/O Pins [DATA_NEEDED: I/O pin count for 208-pin RQFP] β€”
Package 208-pin RQFP (Power Quad Flat Pack) 208-RQFP, exposed pad (208-BFQFP)
Operating Temperature Grade Industrial β€”
Technology CMOS EEPROM β€”
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Logic Array Blocks (LABs) β€” 20
Maximum I/O Pins β€” 132
Propagation Delay (tPD max) β€” 20 ns
Supply Voltage (VCCINT) β€” 4.75 V to 5.25 V
Programming Technology β€” EEPROM, in-system programmable (ISP)
Boundary-Scan Interface β€” IEEE Std. 1149.1 (JTAG)
Operating Temperature β€” 0 Β°C to 70 Β°C (commercial)
Architecture β€” Multiple Array Matrix (MAX), 3rd generation
Process Technology β€” CMOS, 5.0 V EEPROM
Reprogrammability β€” Yes, unlimited ISP cycles

Datasheets & Resources

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