EPM9320RI208-20N vs EPM9320RI208-20 Comparison
Detailed side-by-side comparison of EPM9320RI208-20N by Altera and EPM9320RI208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320RI208-20N
EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera
EPM9320RI208-20N NrndIntel
EPM9320RI208-20
EPM9320RI208-20 - MAX 9000 CPLD, 320 Macrocells, 20ns | Intel
EPM9320RI208-20 ObsoleteSpecification Comparison
| Parameter | EPM9320RI208-20N | EPM9320RI208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $18.95 |
| Device Family | MAX 9000 (EPM9320) | β |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | β |
| Macrocells | 320 | 320 |
| Flip-Flops | 484 | β |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Supply Voltage (VCC) | 5.0 V | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable | β |
| Package | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Package Lead Pitch | 0.500 mm | β |
| Number of Terminals | 208 | β |
| Operating Temperature Range | -40C to +85C (Industrial) | β |
| In-System Programmability | Yes, 5.0 V ISP via JTAG | Yes - IEEE 1149.1 JTAG, 5.0-V ISP |
| JTAG Interface | IEEE Std. 1149.1 compliant | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Dedicated Input Pins | 4 (low-skew global distribution) | 4 (low-skew global) |
| Minimum DC Input on I/O Pins | -0.5 V | β |
| Minimum DC Input on Dedicated Inputs | -0.3 V | β |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 6,000 |
| Maximum Operating Frequency | β | 100 MHz |
| Logic Elements / LABs | β | 20 Logic Array Blocks (16 macro cells each) |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA) |
| User I/O Pins | β | [DATA_NEEDED: I/O pin count for 208-pin RQFP] |
| Operating Temperature Grade | β | Industrial |
| Technology | β | CMOS EEPROM |
| MSL Level | β | [DATA_NEEDED: MSL rating] |