EPM9400LC84-15 vs EPM9400LC84-20 Comparison

Detailed side-by-side comparison of EPM9400LC84-15 by Altera and EPM9400LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9400LC84-15 EPM9400LC84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $23.10 $38.50
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 8,000 8,000 (6,000 to 12,000 typical range)
Macro Cells 400 β€”
Logic Array Blocks 25 β€”
Maximum User I/Os 59 β€”
Maximum Operating Frequency 117.6 MHz β€”
Speed Grade -15 (15 ns pin-to-pin delay) β€”
Core Supply Voltage (VCCINT) 5.0 V β€”
Input Logic Compatibility TTL, 3.3 V and 5.0 V tolerant β€”
Configuration Memory EEPROM (non-volatile, in-system programmable) β€”
JTAG Interface IEEE Std. 1149.1 compliant (ISP) β€”
Package 84-pin PLCC 84-pin PLCC (Plastic Leaded Chip Carrier)
Mounting Type Surface Mount Surface Mount (PLCC socket or SMT land pattern)
Operating Temperature 0C to +70C (Commercial) Commercial (0C to +70C) - assumed from -20 speed grade
Minimum VCCINT 4.75 V β€”
Programming Method In-System Programmable via JTAG β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Architecture β€” Multiple Array Matrix (MAX), 3rd generation, EEPROM-based
Macrocells β€” 400
Flip-Flops β€” 580
Maximum User I/O β€” 55
Pin-to-Pin Propagation Delay β€” 20 ns (speed grade -20)
Maximum Counter Frequency β€” 144 MHz
Supply Voltage (VCCINT) β€” 5 V
I/O Voltage (VCCIO) β€” 3.3 V or 5 V (configurable)
In-System Programming β€” Yes (IEEE 1149.1 JTAG)
Process Technology β€” CMOS EEPROM

Datasheets & Resources

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