EPM9400LC84-20 vs EPM9320LC84-20 Comparison

Detailed side-by-side comparison of EPM9400LC84-20 by Altera and EPM9320LC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9400LC84-20 EPM9320LC84-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $38.50 $9.75
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Architecture Multiple Array Matrix (MAX), 3rd generation, EEPROM-based Multiple Array MatriX (MAX), 3rd generation
Macrocells 400 320
Usable Gates 8,000 (6,000 to 12,000 typical range) β€”
Flip-Flops 580 β€”
Maximum User I/O 55 β€”
Pin-to-Pin Propagation Delay 20 ns (speed grade -20) β€”
Maximum Counter Frequency 144 MHz β€”
Supply Voltage (VCCINT) 5 V β€”
I/O Voltage (VCCIO) 3.3 V or 5 V (configurable) β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Package 84-pin PLCC (Plastic Leaded Chip Carrier) PLCC-84 (Plastic Leaded Chip Carrier)
Process Technology CMOS EEPROM β€”
Operating Temperature Commercial (0C to +70C) - assumed from -20 speed grade 0 C to 70 C
Mounting Type Surface Mount (PLCC socket or SMT land pattern) β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
User I/Os β€” 60
Logic Family β€” CMOS (EEPROM-based)
Pins β€” 84
Propagation Delay (tPD) β€” 16 ns
Internal Counter Frequency β€” 118 MHz
Supply Voltage β€” 5.0 V
In-System Programmability β€” Yes (IEEE 1149.1 JTAG)
Dedicated Inputs β€” 4 (global clock / clear / OE)
PCI Compliance β€” PCI Local Bus Specification Rev. 2.2

Datasheets & Resources

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