EPM9400RC208-20 vs EPM9320RC208-20N Comparison
Detailed side-by-side comparison of EPM9400RC208-20 by Altera and EPM9320RC208-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9400RC208-20
EPM9400RC208-20 - MAX 9000 CPLD 400 Macro Cells 20ns | Altera
EPM9400RC208-20 ObsoleteAltera
EPM9320RC208-20N
EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera
EPM9320RC208-20N ObsoleteSpecification Comparison
| Parameter | EPM9400RC208-20 | EPM9320RC208-20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $60.49 | $0.00 |
| Family | MAX 9000 | β |
| Programmable Type | In System Programmable (ISP) | β |
| Macro Cells | 400 | 320 |
| Usable Gates | 8,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 20 ns | β |
| Maximum Operating Frequency | 100 MHz | 100 MHz |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | β |
| Configuration Technology | EEPROM-based (non-volatile) | β |
| JTAG Interface | IEEE Std. 1149.1 | β |
| Package | 208-pin RQFP (28x28 mm) | 208-pin RQFP (PowerQuad II) |
| Supplier Device Package | 208-RQFP | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Speed Grade | -20 (20 ns) | β |
| Device Family | β | MAX 9000 |
| Logic Type | β | Complex Programmable Logic Device (CPLD) |
| Logic Array Blocks | β | 20 |
| Maximum Pin-to-Pin Delay (tPD) | β | 20 ns |
| Supply Voltage | β | 5.0 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| User I/O Pins | β | 168 |
| Lead Finish | β | [DATA_NEEDED: lead finish] |