EPM9480RC208-15 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9480RC208-15 by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9480RC208-15
EPM9480RC208-15 - 480 Macro Cell MAX 9000 CPLD, 15ns | Intel
EPM9480RC208-15 ObsoleteAltera
EPM9560RC208-15
EPM9560RC208-15 - MAX 9000 CPLD 560 Macro Cells 5V | Altera
EPM9560RC208-15 ObsoleteSpecification Comparison
| Parameter | EPM9480RC208-15 | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.95 | $0.00 |
| Family | MAX 9000 | MAX 9000 |
| Logic Cells / Macro Cells | 480 macro cells | β |
| Usable Gates | 10,000 gates | 12,000 gates |
| Maximum Operating Frequency | 117.6 MHz | β |
| Propagation Delay (tPD) | 15 ns | β |
| User I/O Pins | 153 | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Programmability | In-System (ISP) via JTAG IEEE 1149.1 | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| Package | RQFP-208 | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature | -40C to +85C (commercial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | Third-generation Multiple Array MatriX (MAX) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Device Type | β | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | β | 560 macro cells |
| Pin-to-Pin Delay | β | 15 ns |
| Counter Speed | β | 117.6 MHz |
| Configuration Technology | β | EEPROM (non-volatile) |
| In-System Programmability | β | Yes, via IEEE Std. 1149.1 JTAG |
| Number of I/O Pins | β | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | β | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | β | -15 (15 ns pin-to-pin) |