EPM9480RC240-20 vs EPM9560R1208-20 Comparison
Detailed side-by-side comparison of EPM9480RC240-20 by Altera and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9480RC240-20
EPM9480RC240-20 - 480-Macrocell MAX 9000 CPLD, 240-RQFP | Altera
EPM9480RC240-20 NrndAltera
EPM9560R1208-20
EPM9560R1208-20 - MAX 9000 CPLD 6k Gates 1208-pin | Altera
EPM9560R1208-20 ObsoleteSpecification Comparison
| Parameter | EPM9480RC240-20 | EPM9560R1208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.40 | $22.40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 480 | 560 |
| Usable Gates | 10,000 | 6,000 |
| Logic Elements | 30 | β |
| User I/O Pins | 175 | β |
| Number of Terminals | 240 | β |
| Package | 240-RQFP (32x32 mm, FQFP, Gull Wing) | R-1208 (BGA-style fine-pitch) |
| Maximum Propagation Delay (tpd) | 20 ns | β |
| Maximum Internal Frequency (fMAX, related -C variant) | 100 MHz | β |
| Programmable Flip-Flops (family) | 676 | β |
| Internal Supply Voltage | 4.75 V to 5.25 V | β |
| I/O Signaling Levels | 3.3 V or 5 V (configurable) | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM, third-generation MAX architecture |
| Programming Interface | In-System Programmable (ISP) via IEEE 1149.1 JTAG | β |
| Operating Temperature Grade | Commercial | β |
| Terminal Form | Gull Wing | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| Logic Array Blocks | β | 52 (typical for 560 macrocells) |
| Maximum User I/O | β | 212 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Frequency (fMAX) | β | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature | β | 0C to +70C (commercial) |
| Mounting Type | β | Surface Mount |
| Architecture | β | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | β | JTAG IEEE Std. 1149.1 |
| Configuration Memory | β | On-chip EEPROM (non-volatile) |