EPM9560ARC208-10 vs EPM9320RC208-15 Comparison

Detailed side-by-side comparison of EPM9560ARC208-10 by Intel and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560ARC208-10

EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel

EPM9560ARC208-10 Obsolete
Altera
EPM9320RC208-15

EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera

EPM9320RC208-15 Obsolete

Specification Comparison

Parameter EPM9560ARC208-10 EPM9320RC208-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Device Family MAX 9000A (Multiple Array MatriX) MAX 9000
Programmable Logic Type CPLD (Complex Programmable Logic Device) β€”
Usable Gates 12,000 gates 6,000
Macrocells 560 macrocells β€”
Logic Array Blocks 35 LABs [DATA_NEEDED: LAB count]
User I/O Pins 153 I/O β€”
Propagation Delay (tPD) 10 ns (speed grade -10) β€”
Internal Frequency 144.9 MHz β€”
Supply Voltage 5.0 V 5.0 V
Logic Family CMOS β€”
Configuration Technology EEPROM (non-volatile, in-system programmable) EEPROM-based (non-volatile)
JTAG Interface IEEE 1149.1 boundary-scan (ISP) IEEE Std. 1149.1
Operating Temperature 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range]
Package 208-pin RQFP (PowerQuad Flat Pack) with exposed pad 208-pin RQFP (Power QFP)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Pin Count 208 pins β€”
Macro Cells β€” 320
Pin-to-Pin Propagation Delay β€” 15 ns (speed grade -15)
Maximum Clock Frequency β€” 117.6 MHz
In-System Programmability β€” Yes (ISP via JTAG)
Package Type β€” 208-BFQFP Exposed Pad
Number of I/O Pins β€” [DATA_NEEDED: user I/O count]
Lifecycle Status β€” Obsolete (PDN0706, 2007)

Datasheets & Resources

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