EPM9560ARC208-10 vs EPM9560R1208-20 Comparison
Detailed side-by-side comparison of EPM9560ARC208-10 by Intel and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560ARC208-10 | EPM9560R1208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $22.40 |
| Device Family | MAX 9000A (Multiple Array MatriX) | β |
| Programmable Logic Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 12,000 gates | 6,000 |
| Macrocells | 560 macrocells | 560 |
| Logic Array Blocks | 35 LABs | 52 (typical for 560 macrocells) |
| User I/O Pins | 153 I/O | β |
| Propagation Delay (tPD) | 10 ns (speed grade -10) | 20 ns |
| Internal Frequency | 144.9 MHz | β |
| Supply Voltage | 5.0 V | β |
| Logic Family | CMOS | β |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | β |
| JTAG Interface | IEEE 1149.1 boundary-scan (ISP) | β |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Package | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad | R-1208 (BGA-style fine-pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| Pin Count | 208 pins | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | β | 212 |
| Maximum Frequency (fMAX) | β | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Process Technology | β | CMOS EEPROM, third-generation MAX architecture |
| Architecture | β | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| Boundary-Scan Test | β | JTAG IEEE Std. 1149.1 |
| Configuration Memory | β | On-chip EEPROM (non-volatile) |