EPM9560ARC208-10N vs EPM9480RC208-15 Comparison

Detailed side-by-side comparison of EPM9560ARC208-10N by Altera and EPM9480RC208-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM9560ARC208-10N

EPM9560ARC208-10N - MAX 9000 CPLD 560 Macro 208-RQFP | Altera

EPM9560ARC208-10N Obsolete
Intel
EPM9480RC208-15

EPM9480RC208-15 - 480 Macro Cell MAX 9000 CPLD, 15ns | Intel

EPM9480RC208-15 Obsolete

Specification Comparison

Parameter EPM9560ARC208-10N EPM9480RC208-15
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $27.20 $24.95
Family MAX 9000 MAX 9000
Macrocells 560 β€”
Usable Gates 12,000 10,000 gates
User I/O Pins 153 153
Pin-to-Pin Delay 10 ns β€”
Internal Counter Frequency 144.9 MHz β€”
Supply Voltage 5 V 5.0 V
Technology CMOS EEPROM β€”
Package 208-pin RQFP (PowerQuad II) RQFP-208
Mounting Type Surface Mount Surface Mount
Operating Temperature 0 C to +70 C (commercial) -40C to +85C (commercial)
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
In-System Programmability Yes (JTAG ISP) β€”
Logic Array Blocks (LABs) 20 β€”
Speed Grade -10 β€”
RoHS Status Compliant (N suffix) [DATA_NEEDED: RoHS compliance status]
Lead Finish [DATA_NEEDED: lead finish] β€”
MSL Level [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Logic Cells / Macro Cells β€” 480 macro cells
Maximum Operating Frequency β€” 117.6 MHz
Propagation Delay (tPD) β€” 15 ns
Programmability β€” In-System (ISP) via JTAG IEEE 1149.1
Architecture β€” Multiple Array MatriX (MAX) - 3rd generation

Datasheets & Resources

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