EPM9560ARC240-10 vs EPM9560ARC208-10 Comparison

Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC240-10 EPM9560ARC208-10
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $28.80 $0.00
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Architecture Multiple Array MatriX (MAX) - third generation β€”
Usable Gates 12,000 12,000 gates
Macrocells 560 560 macrocells
User I/Os (this package) 191 (per Mouser listing) β€”
Internal Frequency 144.9 MHz 144.9 MHz
Propagation Delay (tpd) 11.4 ns β€”
Supply Voltage - Internal (VCCINT) 5.0 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) β€”
Process Technology CMOS EEPROM β€”
Package 240-pin PowerQuad QFP (RQFP / EAR240) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Operating Temperature 0C to +70C (commercial) 0 C to +70 C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) β€”
Logic Family CMOS CMOS
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family β€” MAX 9000A (Multiple Array MatriX)
Programmable Logic Type β€” CPLD (Complex Programmable Logic Device)
Logic Array Blocks β€” 35 LABs
User I/O Pins β€” 153 I/O
Propagation Delay (tPD) β€” 10 ns (speed grade -10)
Supply Voltage β€” 5.0 V
Configuration Technology β€” EEPROM (non-volatile, in-system programmable)
JTAG Interface β€” IEEE 1149.1 boundary-scan (ISP)
Mounting Type β€” Surface Mount
Pin Count β€” 208 pins

Datasheets & Resources

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