EPM9560ARC240-10 vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARC240-10
EPM9560ARC240-10 - MAX 9000 CPLD 560 Macrocells 144.9MHz | Altera
EPM9560ARC240-10 ObsoleteAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560ARC240-10 | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.80 | $115.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EE PLD (CMOS EEPROM-based CPLD) |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) |
| Usable Gates | 12,000 | β |
| Macrocells | 560 | β |
| User I/Os (this package) | 191 (per Mouser listing) | β |
| Internal Frequency | 144.9 MHz | β |
| Propagation Delay (tpd) | 11.4 ns | 15 ns (speed grade -15) |
| Supply Voltage - Internal (VCCINT) | 5.0 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (selectable) | β |
| Process Technology | CMOS EEPROM | β |
| Package | 240-pin PowerQuad QFP (RQFP / EAR240) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | β |
| Logic Family | CMOS | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Mounting Type | β | Through-Hole |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |