EPM9560ARC240-10N vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560ARC240-10N by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARC240-10N
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N ObsoleteAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560ARC240-10N | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.50 | $115.00 |
| Logic Family | MAX 9000 (CPLD) | β |
| Process Technology | CMOS EEPROM | β |
| Macro Cells | 560 | 560 |
| User I/Os | 191 | β |
| Logic Array Blocks (LABs) | 16 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Internal Frequency (fMAX) | 145 MHz | β |
| Supply Voltage (VCCINT) | 5.0 V | β |
| Operating Temperature | 0Β°C to +70Β°C (Commercial) | β |
| Package | 240-pin RQFP (32x32 mm) | β |
| Mounting Type | Surface Mount | Through-Hole |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster | β |
| Programmability | In-system, EEPROM-based (non-volatile) | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| I/O Standard | 5.0 V TTL-compatible | β |
| RoHS Status | Non-RoHS (legacy Altera part) | Non-compliant (ceramic CPGA, contains lead) |
| Family | MAX 9000 | MAX 9000 |
| Device Type | β | EE PLD (CMOS EEPROM-based CPLD) |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | β | Multiple Array MatriX (MAX) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |