EPM9560ARC304-10F vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560ARC304-10F by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARC304-10F
EPM9560ARC304-10F - MAX 9000A CPLD 560 Macrocell | Altera
EPM9560ARC304-10F NrndAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560ARC304-10F | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $115.00 |
| Device Family | MAX 9000A | β |
| Programmable Type | In System Programmable (ISP) | β |
| Number of Macrocells | 560 | β |
| Number of Logic Elements/Blocks | 35 LABs | β |
| Number of Gates | 12000 | β |
| Number of I/O | 216 | β |
| Maximum Delay Time (tPD) | 10 ns | β |
| Supply Voltage (Internal) | 4.75 V to 5.25 V | β |
| Operating Temperature | 0 C to +70 C (commercial) | β |
| Package | 304-pin RQFP (PowerQuad II) | β |
| Package Code | FQFP | β |
| Terminal Form | Gull Wing | β |
| Package Shape | Square | β |
| Mounting Type | Surface Mount | Through-Hole |
| Configuration Memory | EEPROM (non-volatile) | β |
| JTAG Support | IEEE 1149.1 (ISP) | β |
| RoHS Status | RoHS | Non-compliant (ceramic CPGA, contains lead) |
| Speed Grade | -10 (10 ns) | β |
| Family | β | MAX 9000 |
| Device Type | β | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | β | Multiple Array MatriX (MAX) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |