EPM9560ARI240-10 vs EPM9560ARI240-10N Comparison
Detailed side-by-side comparison of EPM9560ARI240-10 by Altera and EPM9560ARI240-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560ARI240-10N NrndSpecification Comparison
| Parameter | EPM9560ARI240-10 | EPM9560ARI240-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $105.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | β |
| User I/O Pins | 191 | β |
| Package | 240-pin RQFP (PowerQuad Flat Pack) | 240-pin RQFP (RQFP-240 / PQFP-240) |
| Pin-to-Pin Propagation Delay | 10 ns | β |
| Internal Frequency | 144.9 MHz | β |
| Supply Voltage | 5.0 V | 5.0 V nominal (4.5 V min, 5.5 V max) |
| Technology | CMOS, EEPROM-based configuration | β |
| Operating Temperature Range | -40 C to +85 C (industrial) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, instant-on) | β |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | β |
| Number of Terminals | 240 | β |
| Terminal Form | Gull Wing | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/Os | β | 216 (per digchip); 191 (per Mouser) |
| Maximum Internal Frequency | β | 144.9 MHz (typical); 145 MHz (per digchip) |
| Propagation Delay (tPD) | β | 10 ns (-10 speed grade) |
| Logic Family | β | CMOS, EEPROM-based |
| In-System Programmability | β | Yes (5.0 V ISP via JTAG) |
| Operating Temperature | β | -40C to +85C (industrial) |
| Architecture | β | Multiple Array MatriX (MAX) - 3rd generation |
| JTAG (IEEE 1149.1) | β | Yes |
| Lead-Free / RoHS | β | [DATA_NEEDED: lead-free / RoHS status not in provided data] |