EPM9560ARI240-10 vs EPM9560GC280-15N Comparison
Detailed side-by-side comparison of EPM9560ARI240-10 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARI240-10
EPM9560ARI240-10 - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560ARI240-10 ObsoleteIntel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndSpecification Comparison
| Parameter | EPM9560ARI240-10 | EPM9560GC280-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $125.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 12,000 | 12,000 (typical) |
| Macro Cells | 560 | β |
| User I/O Pins | 191 | β |
| Package | 240-pin RQFP (PowerQuad Flat Pack) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Pin-to-Pin Propagation Delay | 10 ns | β |
| Internal Frequency | 144.9 MHz | β |
| Supply Voltage | 5.0 V | β |
| Technology | CMOS, EEPROM-based configuration | β |
| Operating Temperature Range | -40 C to +85 C (industrial) | β |
| Mounting Type | Surface Mount | β |
| Configuration Memory | EEPROM (non-volatile, instant-on) | β |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | β |
| Number of Terminals | 240 | β |
| Terminal Form | Gull Wing | PIN/PEG |
| Device Family | β | MAX 9000 |
| Product Type | β | EE PLD / CPLD |
| Macrocell Count | β | 560 |
| Propagation Delay (tPD) | β | 16.6 ns |
| Maximum Clock Frequency | β | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Maximum Supply Voltage | β | 5.25 V |
| Logic Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (5.0-V ISP via JTAG) |
| Boundary-Scan (JTAG) | β | IEEE Std. 1149.1 compliant |
| Package Code | β | PGA / CPGA280 |
| Operating Temperature Grade | β | Commercial |
| Architecture | β | Multiple Array MatriX (MAX) 3rd generation |