EPM9560GC280-15 vs EPM9560ABC356-10 Comparison

Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560ABC356-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GC280-15 EPM9560ABC356-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $115.00 $92.40
Family MAX 9000 β€”
Device Type EE PLD (CMOS EEPROM-based CPLD) β€”
Macro Cells 560 β€”
Typical Gates 12,000 β€”
Maximum Operating Frequency 117.6 MHz β€”
Propagation Delay (tpd) 15 ns (speed grade -15) β€”
Propagation Delay (alternate datasheet figure) 16.6 ns β€”
Supply Voltage (VCCINT/VCCIO) 5.0 V β€”
Operating Temperature (Commercial) 0C to +70C β€”
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) β€”
Mounting Type Through-Hole Surface Mount
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 EEPROM, 5-V In-System Programmable (ISP)
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) β€”
Architecture Multiple Array MatriX (MAX) β€”
RoHS Status Non-compliant (ceramic CPGA, contains lead) [DATA_NEEDED: rohs status]
Lifecycle Status Obsolete (legacy Altera MAX 9000 family) β€”
Device Family β€” MAX 9000A
Product Series β€” MAX 9000
Macrocells β€” 560
Usable Gates β€” 12,000
Logic Array Blocks (LABs) β€” 35
Maximum User I/Os β€” 216
Pin-to-Pin Delay (tPD) β€” 10 ns
Maximum Counter Frequency β€” 144 MHz
Supply Voltage β€” 4.75 V to 5.25 V (5 V nominal)
JTAG Interface β€” IEEE Std. 1149.1 compliant
PCI Compliance β€” PCI Local Bus Specification Revision 2.2
Operating Temperature β€” 0 Β°C to 70 Β°C (Commercial)
Package β€” 356-LBGA (35 x 35 mm)

Datasheets & Resources

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