EPM9560GC280-15 vs EPM9560ARI240-10N Comparison
Detailed side-by-side comparison of EPM9560GC280-15 by Altera and EPM9560ARI240-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteIntel
EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
EPM9560ARI240-10N NrndSpecification Comparison
| Parameter | EPM9560GC280-15 | EPM9560ARI240-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $115.00 | $105.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (CMOS EEPROM-based CPLD) | β |
| Macro Cells | 560 | β |
| Typical Gates | 12,000 | β |
| Maximum Operating Frequency | 117.6 MHz | β |
| Propagation Delay (tpd) | 15 ns (speed grade -15) | β |
| Propagation Delay (alternate datasheet figure) | 16.6 ns | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Operating Temperature (Commercial) | 0C to +70C | β |
| Package Type | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | β |
| Mounting Type | Through-Hole | Surface Mount |
| Programmability | In-System Programmable (ISP) via JTAG IEEE 1149.1 | β |
| Technology | CMOS EEPROM, 0.5 um process (MAX third-gen) | β |
| Architecture | Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - 3rd generation |
| RoHS Status | Non-compliant (ceramic CPGA, contains lead) | β |
| Lifecycle Status | Obsolete (legacy Altera MAX 9000 family) | β |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 12,000 |
| Macrocells | β | 560 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/Os | β | 216 (per digchip); 191 (per Mouser) |
| Maximum Internal Frequency | β | 144.9 MHz (typical); 145 MHz (per digchip) |
| Propagation Delay (tPD) | β | 10 ns (-10 speed grade) |
| Supply Voltage | β | 5.0 V nominal (4.5 V min, 5.5 V max) |
| Logic Family | β | CMOS, EEPROM-based |
| In-System Programmability | β | Yes (5.0 V ISP via JTAG) |
| Package | β | 240-pin RQFP (RQFP-240 / PQFP-240) |
| Operating Temperature | β | -40C to +85C (industrial) |
| JTAG (IEEE 1149.1) | β | Yes |
| Lead-Free / RoHS | β | [DATA_NEEDED: lead-free / RoHS status not in provided data] |