EPM9560GC280-15N vs EPM9320GC280-15 Comparison
Detailed side-by-side comparison of EPM9560GC280-15N by Intel and EPM9320GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndAltera
EPM9320GC280-15
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GC280-15N | EPM9320GC280-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $92.50 |
| Device Family | MAX 9000 | β |
| Product Type | EE PLD / CPLD | β |
| Macrocell Count | 560 | β |
| Usable Gates | 12,000 (typical) | 6,000 |
| Propagation Delay (tPD) | 16.6 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Maximum Supply Voltage | 5.25 V | β |
| Logic Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | β |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | β |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Package Code | PGA / CPGA280 | β |
| Terminal Form | PIN/PEG | β |
| Operating Temperature Grade | Commercial | β |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Family | β | MAX 9000 (EPM9320) |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | 20 (16 macrocells per LAB) |
| Pin-to-Pin Propagation Delay | β | 15 ns |
| Maximum Internal Frequency | β | 117.6 MHz |
| Maximum User I/O Pins | β | 164 |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| I/O Voltage Levels | β | 3.3 V or 5 V (configurable) |
| Programmability | β | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| Mounting Type | β | Through-hole (PGA socket) |
| Operating Temperature | β | 0 C to +70 C (commercial) |
| MSL Level | β | 3 (168 hours) |
| RoHS Status | β | ROHS3 compliant (per fpgalink listing) |
| Technology Node | β | CMOS EEPROM, third-generation MAX |