EPM9560GC280-15N vs EPM9560ARI240-10 Comparison
Detailed side-by-side comparison of EPM9560GC280-15N by Intel and EPM9560ARI240-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndAltera
EPM9560ARI240-10
EPM9560ARI240-10 - MAX 9000 CPLD 560 Macro Cells | Altera
EPM9560ARI240-10 ObsoleteSpecification Comparison
| Parameter | EPM9560GC280-15N | EPM9560ARI240-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $0.00 |
| Device Family | MAX 9000 | β |
| Product Type | EE PLD / CPLD | β |
| Macrocell Count | 560 | β |
| Usable Gates | 12,000 (typical) | 12,000 |
| Propagation Delay (tPD) | 16.6 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Maximum Supply Voltage | 5.25 V | β |
| Logic Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | β |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | β |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | 240-pin RQFP (PowerQuad Flat Pack) |
| Package Code | PGA / CPGA280 | β |
| Terminal Form | PIN/PEG | Gull Wing |
| Operating Temperature Grade | Commercial | β |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | β |
| Family | β | MAX 9000 |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 560 |
| User I/O Pins | β | 191 |
| Pin-to-Pin Propagation Delay | β | 10 ns |
| Internal Frequency | β | 144.9 MHz |
| Supply Voltage | β | 5.0 V |
| Technology | β | CMOS, EEPROM-based configuration |
| Operating Temperature Range | β | -40 C to +85 C (industrial) |
| Mounting Type | β | Surface Mount |
| Configuration Memory | β | EEPROM (non-volatile, instant-on) |
| Logic Architecture | β | Multiple Array MatriX (MAX) with global interconnect array |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | β | [DATA_NEEDED: MSL level] |
| Number of Terminals | β | 240 |