EPM9560GC280-15N vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560GC280-15N by Intel and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560GC280-15N
EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
EPM9560GC280-15N NrndAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GC280-15N | EPM9560GC280-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $125.00 | $115.00 |
| Device Family | MAX 9000 | β |
| Product Type | EE PLD / CPLD | β |
| Macrocell Count | 560 | β |
| Usable Gates | 12,000 (typical) | β |
| Propagation Delay (tPD) | 16.6 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | 5.0 V |
| Maximum Supply Voltage | 5.25 V | β |
| Logic Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | β |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant | β |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) | β |
| Package Code | PGA / CPGA280 | β |
| Terminal Form | PIN/PEG | β |
| Operating Temperature Grade | Commercial | β |
| Architecture | Multiple Array MatriX (MAX) 3rd generation | Multiple Array MatriX (MAX) |
| Family | β | MAX 9000 |
| Device Type | β | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Mounting Type | β | Through-Hole |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| RoHS Status | β | Non-compliant (ceramic CPGA, contains lead) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |