EPM9560GM280-15 vs EPM9560GC280-15 Comparison
Detailed side-by-side comparison of EPM9560GM280-15 by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560GM280-15
EPM9560GM280-15 - 560 Macrocells MAX 9000 PLD 5V | Altera
EPM9560GM280-15 NrndAltera
EPM9560GC280-15
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpecification Comparison
| Parameter | EPM9560GM280-15 | EPM9560GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $110.00 | $115.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (EEPROM-based) | EE PLD (CMOS EEPROM-based CPLD) |
| Macrocells | 560 | β |
| Flip-Flops | 772 | β |
| User I/O | 216 | β |
| Logic Array Blocks (LABs) | 35 (16 macrocells each) | β |
| Supply Voltage (Nominal) | 5.0 V | β |
| Supply Voltage (Max) | 5.5 V | β |
| I/O Logic Level Support | 3.3 V or 5 V | β |
| Pin-to-Pin Delay (tPD) | 15 ns (speed grade -15) | β |
| Package | FineLine BGA-280 (GM) | β |
| Process Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (5V ISP via JTAG IEEE 1149.1) | β |
| Operating Temperature | -40C to +85C (industrial) | β |
| RoHS Status | ROHS3 Compliant | Non-compliant (ceramic CPGA, contains lead) |
| MSL Level | 3 (168 Hours) | β |
| Macro Cells | β | 560 |
| Typical Gates | β | 12,000 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Propagation Delay (tpd) | β | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | β | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Package Type | β | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Mounting Type | β | Through-Hole |
| Programmability | β | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | β | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | β | Multiple Array MatriX (MAX) |
| Lifecycle Status | β | Obsolete (legacy Altera MAX 9000 family) |