EPM9560R1208-20 vs EPM9560ARC208-10 Comparison
Detailed side-by-side comparison of EPM9560R1208-20 by Altera and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560R1208-20
EPM9560R1208-20 - MAX 9000 CPLD 6k Gates 1208-pin | Altera
EPM9560R1208-20 ObsoleteIntel
EPM9560ARC208-10
EPM9560ARC208-10 - MAX 9000 CPLD 560 Macro 208-RQFP | Intel
EPM9560ARC208-10 ObsoleteSpecification Comparison
| Parameter | EPM9560R1208-20 | EPM9560ARC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $22.40 | $0.00 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Usable Gates | 6,000 | 12,000 gates |
| Macrocells | 560 | 560 macrocells |
| Logic Array Blocks | 52 (typical for 560 macrocells) | 35 LABs |
| Maximum User I/O | 212 | β |
| Propagation Delay (tPD) | 20 ns | 10 ns (speed grade -10) |
| Maximum Frequency (fMAX) | 125 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Package | R-1208 (BGA-style fine-pitch) | 208-pin RQFP (PowerQuad Flat Pack) with exposed pad |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS EEPROM, third-generation MAX architecture | β |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) | β |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1 | β |
| Configuration Memory | On-chip EEPROM (non-volatile) | β |
| RoHS Status | [DATA_NEEDED: confirm via current distributor data] | [DATA_NEEDED: RoHS status] |
| Device Family | β | MAX 9000A (Multiple Array MatriX) |
| Programmable Logic Type | β | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | β | 153 I/O |
| Internal Frequency | β | 144.9 MHz |
| Supply Voltage | β | 5.0 V |
| Logic Family | β | CMOS |
| Configuration Technology | β | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | β | IEEE 1149.1 boundary-scan (ISP) |
| Pin Count | β | 208 pins |