EPM9560RC-15 vs EPM9560R1208-20 Comparison
Detailed side-by-side comparison of EPM9560RC-15 by Altera and EPM9560R1208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560RC-15 - 560-Macrocell MAX 9000 CPLD, 15ns, 240-RQFP | Altera / Intel
EPM9560RC-15 β Last Time BuySpecification Comparison
| Parameter | EPM9560RC-15 | EPM9560R1208-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $30.10 | $22.40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 6,000 |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | β |
| Maximum User I/O Pins | 191 | β |
| Pin-to-Pin Delay (tPD1) | 15 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | β |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Package | 240-pin RQFP (32x32 mm) | R-1208 (BGA-style fine-pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | β |
| Process Technology | CMOS EEPROM | CMOS EEPROM, third-generation MAX architecture |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm via current distributor data] |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | Yes (IEEE 1149.1 JTAG) |
| Logic Array Blocks | β | 52 (typical for 560 macrocells) |
| Maximum User I/O | β | 212 |
| Propagation Delay (tPD) | β | 20 ns |
| Maximum Frequency (fMAX) | β | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 5.0 V |
| Technology | β | CMOS EEPROM |
| Boundary-Scan Test | β | JTAG IEEE Std. 1149.1 |
| Configuration Memory | β | On-chip EEPROM (non-volatile) |